diff --git a/MedAP/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache b/MedAP/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache
index 6474837..4f8bed1 100644
Binary files a/MedAP/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache and b/MedAP/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache differ
diff --git a/MedAP_data/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache b/MedAP_data/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache
index dc05ac0..3681666 100644
Binary files a/MedAP_data/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache and b/MedAP_data/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache differ
diff --git a/VersGen/VersGen.csproj b/VersGen/VersGen.csproj
index b5d6b05..ba7adfb 100644
--- a/VersGen/VersGen.csproj
+++ b/VersGen/VersGen.csproj
@@ -9,7 +9,7 @@
     <AppDesignerFolder>Properties</AppDesignerFolder>
     <RootNamespace>VersGen</RootNamespace>
     <AssemblyName>VersGen</AssemblyName>
-    <TargetFrameworkVersion>v4.5.2</TargetFrameworkVersion>
+    <TargetFrameworkVersion>v4.6.2</TargetFrameworkVersion>
     <FileAlignment>512</FileAlignment>
   </PropertyGroup>
   <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
diff --git a/VersGen/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache b/VersGen/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache
index a6e1437..814e155 100644
Binary files a/VersGen/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache and b/VersGen/obj/Debug/DesignTimeResolveAssemblyReferencesInput.cache differ